Abstract
To achieve several hundred Amperes of output current in high voltage, two-level, automotive traction inverters with Silicon Carbide MOSFET B6 topology, still, parallelization of chips is required. To ensure high reliability, optimized power densities and efficiency, a balanced electric and thermal stress is crucial. This paper describes the hardware demonstration of the reduced relative thermal imbalance within a system of parallel chips by increased switching speed controlled by gate resistor reduction towards very low values. The benefits are quantified. The laboratory inverter- setup and measurement method by IR camera measurements are described. Some technological backgrounds in this context are discussed.